1. Field of the Invention
This invention relates to sense circuitry and, more particularly, to a sense amplifier having separate cascode devices for precharge and sensing portions of the sense amplifier.
2. Description of the Related Art
The following descriptions and examples are given as background only.
The proliferation of computers and other microprocessor-based devices has contributed to an increasing demand for semiconductor memory. Microprocessors are present not only in computers, but in a diverse range of products including automobiles, cellular telephones and kitchen appliances. A conventional microprocessor executes a sequence of instructions and processes information. Frequently, both the instructions and the information reside in semiconductor memory. Therefore, an increased requirement for memory has accompanied the microprocessor boom. As microprocessors have become more sophisticated, greater capacity and speed are demanded from the associated memory.
There are various types of semiconductor memory, including Read Only Memory (ROM) and Random Access Memory (RAM). ROM is typically used where instructions or data must not be modified, while RAM is used to store instructions or data which must not only be read, but modified. ROM is a form of non-volatile storage—i.e., the information stored in ROM persists even after power is removed from the memory. On the other hand, RAM storage is generally volatile, and must remain powered-up in order to preserve its contents.
A conventional semiconductor memory device stores information digitally, in the form of bits (i.e., binary digits). The memory is typically organized as a matrix of memory cells, each of which is capable of storing one bit. The cells of the memory matrix are accessed by word lines and bit lines. Word lines are typically associated with the rows of the memory matrix, while bit lines are associated with the columns. Raising a word line activates a given row; the bit lines are then used to read from (or write to) the corresponding cells in the currently active row. Memory cells are typically capable of assuming one of two voltage states (commonly described as “on” or “off”). Information is stored in the memory by setting each cell in the appropriate logic state. For example, to store a bit having the value 1 in a particular cell, one would set the state of that cell to “on;” similarly, a 0 would be stored by setting the cell to the off state. (Obviously, the association of “on” with 1 and “off” with 0 is arbitrary, and could be reversed.)
The contents of a memory cell are generally read by applying an input voltage to a selected wordline, and sensing whether the voltage on a selected bitline changes in response to the applied input voltage. In some cases, the bitline acts as a capacitor, and may be precharged to a predetermined voltage before the memory cell is read. When the memory cell is read, the bitline voltage may discharge to ground to indicate a first logic state, or may remain at the precharged voltage to indicate a second logic state. A sense amplifier is generally used to “sense” the logic state present on the selected bitline.
In some cases, a sense amplifier may be included for each column of memory cells in a memory array. The sense amplifiers may be single-ended or differential, depending on the particular configuration of the memory cell. For example, single-ended sense amplifiers may receive only one bitline as input, whereas differential sense amplifiers receive differential bitlines (i.e., a pair of complementary bitlines) as input. Single-ended sense amplifiers and memory cells are generally used to obtain smaller layouts than their differential counterparts, but often do so at the cost of reduced noise margins and operational speed. Though differential sense amplifiers and memory cells provide a somewhat larger layout, they are generally used in high-speed applications that benefit from relatively high common mode noise rejection.
Operational speed is often a primary concern in sense amplifier design. In some cases, the speed of the sense amplifier may be determined by the sensitivity of the sense amplifier to the discharge rate of the bitline. For example, a relatively sensitive sense amplifier may have a relatively high trip-point voltage (i.e., a voltage relatively close to the precharge voltage), which enables the sense amplifier to detect a programmed memory location once the voltage level on the bitline drops by a small amount. On the other hand, a sense amplifier with relatively low sensitivity may have a substantially lower trip-point voltage, which requires a much larger voltage drop on the bitline before a programmed memory location can be detected. Since it generally takes longer to discharge the bitline to a lower trip-point voltage (and to precharge the bitline to the precharge voltage when the bitline is discharged to a lower voltage), a more sensitive sense amplifier may be desired when operational speed is a concern.
Another consideration in sense amplifier design is power consumption. The act of charging and discharging the bitline generally results in power consumption; the greater the swing between precharged and discharged voltage values, the greater the power consumption. Low memory device power consumption is crucial in many devices, including portable computing and telecommunication devices (e.g., portable computers, personal digital assistants, cell phones, etc.). Therefore, the level to which the bitline is precharged is often limited, in some memory devices, to decrease the power consumption by reducing the swing between the precharged and discharged bitline voltage values.
For example, a cascode device may be coupled between the bitline of a memory cell and the output stage of a conventional single-ended sense amplifier. In some cases, a “cascode device” may be defined as a transistor, which is turned “on” and “off” by varying the voltage applied to the source terminal of the transistor, rather than varying the gate voltage. For example, an N-channel cascode transistor may have a source terminal coupled to a bitline, a drain terminal coupled to an input node of the sense amplifier output stage, and a gate terminal coupled to a constant voltage source (e.g., VCC). A pull-up device (or “precharge transistor”) may be coupled to the drain terminal of the cascode transistor for precharging the bitline to a voltage value approximately equal to the value of the constant voltage source minus the threshold voltage (or turn-on voltage) of the cascode transistor. The input of the output stage may also be precharged to VCC. To reduce the precharge voltage swing, the constant voltage source may be some intermediate voltage between ground and VCC. If the selected memory cell is programmed, a drop in the bitline voltage during a read cycle will cause the cascode transistor to switch on, thereby coupling the bitline to the input of the output stage. The voltage at the input of the output stage drops rapidly to the voltage of the bitline through charge sharing.
Unfortunately, a problem with the conventional sense amplifier described above arises when noise on the bitline causes the cascode transistor to inadvertently switch on, resulting in the reading of invalid data. Potential noise sources may include, e.g., capacitive coupling between nearby bitlines in the same layer and/or within adjacent layers of the memory cell. Therefore, a noise margin must be provided to account for noise that can be injected on the bitline. Providing a sufficient noise margin increases the reliability of the data read from the memory cell.